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ddr termination regulator TJ2997 apr, 2011 - r1.0.1 1/13 htc sop8 / sop8-pp pkg ordering information device package TJ2997gd sop8 TJ2997gdp sop8-pp features z source and sink current z low output voltage offset z no external resistors required z linear topology z suspend to ram (str) functionality z low external component count z thermal shutdown z available in sop8, sop8-pp package s application z ddr -ii and -iii termination voltage z sstl termination z hstl termination descripsion the TJ2997 linear regulator is designed to meet the jedec sstl specifications for termination of ddr- sdram. the device contains a high-speed operational am plifier to provide excellent response to load transients. the output stage prevents shoot through wh ile delivering up to 1.5a continuous current and transient peaks up to 3a with respect to pvin operating condition in the application as required for ddr- sdram termination. the TJ2997 also incorporates a v sense pin to provide superior load regulation and a v ref output as a reference for the chipset and dimms. an additional feature found on the TJ2997 is an active high enable (en) pin that provides suspend to ra m (str) functionality. when en is pulled low the v tt output will tri-state providing a high impedance output, but, v ref will remain active. a power savings advantage can be obtained in this mode through lower quiescent current. absolute maximum ratings characteristic symbol min. max. unit supply voltage to gnd pv in av in v ddq -0.3 -0.3 -0.3 6.0 6.0 6.0 v lead temperature (soldering, 10 sec) t sol 260 storage temperature range t stg -65 150 operating junction temperature range t jopr -40 125 recommended operation range characteristic symbol min. max. unit av in to gnd av in 2.3 5.5 v pv in & en to gnd pv in & en 0 av in v ordering information package order no. description package marking supplied as sop8 TJ2997gd ddr termination regulator TJ2997g reel sop8-pp TJ2997gdp ddr termination regulator TJ2997g reel
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 2/13 htc pin configuration gnd en vsense vref vtt pvin avin vddq 1 2 3 4 8 7 6 5 gnd en vsense vref vtt pvin avin vddq 1 2 3 4 8 7 6 5 exposed thermal pad sop8 sop8-pp pin description pin no. pin name pin function 1 gnd ground 2 en enable 3 vsense feedback pin for regulating v tt 4 vref buffered internal reference voltage of v ddq /2 5 vddq input for internal reference equal to v ddq /2 6 avin analog bias input pin 7 pvin power input pin 8 vtt output voltage for connection to termination resistors exposed thermal pad exposed thermal connec tion. connect to ground. (sop8-pp only) typical application v ddq av in pv in v tt v sense v ref gnd en v en v ddq = 1.8v v ref = 0.9v v tt = 0.9v v avin = 2.5v + + 47uf 220uf + 0.1uf
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 3/13 htc electrical characteristics (1) specifications with standard typeface are for t j = 25 ? . unless otherwise specified, avin = 2.5v, pvin = vddq = 1.8v (1), (2), (3) for ddr . avin = 2.5v, pvin = vddq = 1.5v (1), (2), (3) for ddr . parameter symbol test condit ion min. typ. max. unit v ref voltage v ref v ddq = 1.8v 0.882 0.90 0.918 v v ref voltage v ref v ddq = 1.5v 0.735 0.75 0.765 v v tt output voltage v tt i out = 0 a v ddq = 1.8v, pvin = 1.8v i out = 0.9 a (6) v ddq = 1.8v, pvin = 1.8v 0.86 0.86 0.90 0.90 0.94 0.94 v v tt output voltage v tt i out = 0 a @ v ddq = 1.5v, pvin = 1.5v i out = 0.5 a (6) @ v ddq = 1.5v, pvin = 1.5v i out = 0.9a (6) @ v ddq = 1.5v, pvin = 1.8v 0.71 0.71 0.71 0.75 0.75 0.75 0.79 0.79 0.79 v v tt output voltage offset v osvtt i out = 0 a i out = 0.5 a (6) i out = 0.9 a (6) (if applicable) -25 -25 -25 0 0 0 25 25 25 mv quiescent current (4) i q i out = 0a - 250 500 ua v ddq input impedance z vddq - 100 - k ? quiescent current in shutdown (4) i sd en = 0v 150 300 ua shutdown leakage current i q_sd en = 0v 0.1 0.5 ua minimum enable high level v ih 1.9 (7) - - v maximum enable low level v il - - 0.6 v v tt leakage current in shutdown i v en= 0v, v tt = 1.25v 1 10 ua v sense input current i sense - - 0.1 ua thermal shutdown (5) t sd - 165 - note 1. absolute maximum ratings indicate limits beyond which damage to the device may occur. o perating range indicates conditi ons for which the device is intended to be functional, but does not guarantee specific performance limits. for guaranteed specifications and test conditions see electrical characteristi cs. the guaranteed specifications apply only for the test condit ions listed. some performance characteristics may degrade when th e device is not operated under the listed test conditions. note 2. at elevated temperatures, devices must be derated based on thermal resistance. the device in the sop8 package must be derated at ja = 165 ? c/w junction to ambient with no heat sink. note 3. limits are 100% production tested at 25 ? c. limits over the operating temperature range are guaranteed through correlation. note 4. quiescent current defined as the current flow into av in . note 5. the maximum allowable power dissipation is a function of the maximum junction temperature, t j(max), the junction to ambient thermal resistance, ja , and the ambient temperature, t a . exceeding the maximum allowabl e power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. note 6. v tt load regulation is tested by using a 10 ms current pulse and measuring v tt . note 7. in the case of av in > 2.5v, minimum enable high level is av in * 0.7.
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 4/13 htc typical operating characteristics t.b.d.
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 5/13 htc description the TJ2997 is a linear bus termination regulator designed for ddr ii and ddr iii memories. the output, v tt is capable of sinking and sourcing current while regulating the output voltage equal to v ddq / 2. the output stage has been designed to maintain excellent load regulation while preventing shoot through. the TJ2997 also incorporates two distinct power rail s that separate the analog circuitry from the power output stage. this allows a split rail approach to be utilized to decrease internal power dissipation. it also permits the TJ2997 to provide a terminatio n solution for the next generation of ddr-sdram memory.. series stub termination logic (sstl) was created to improve signal integrity of the data transmission across the memory bus. this termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with ddr-sdram. the most common form of termination is class ii single pa rallel termination. this involves one r s series resistor from the chipset to the memory and one r t termination resistor. typical values for r s and r t are 25 ohms, although these can be changed to scale the current r equirements from the TJ2997. this implementation can be seen below in figure 1. figure 1. sstl-termination scheme pin description av in and pv in av in and pv in are the input supply pins for the TJ2997. av in is used to supply all the internal control circuitry. pv in , however, is used exclusively to provide the rail voltage for the output stage used to create v tt . these pins have the capability to work off separate supplies depending on the application. higher voltages on pv in will increase the maximum continuous output current because of output r dson limitations at voltages close to v tt . the disadvantage of high values of pvin is that the internal power loss will also increase, ther mally limiting the design. the limitation on input voltage selection is that pv in must be equal to or lower than av in . it is recommended to connect pv in to voltage rails equal to or less than 3.3v to prevent the thermal limit from tripping because of excessive internal power dissi pation. if the junction temperature exceeds the thermal shutdown then the part will ent er a shutdown state where both v tt and v ref are tri-stated. v ddq v ddq is the input used to create the inte rnal reference voltage for regulating v tt . the reference voltage is generated from a resistor divider of two internal 50 k ? resistors. this guarantees that v tt will track v ddq / 2 precisely. the optimal implementation of v ddq is as a remote sense. this can be
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 6/13 htc achieved by connecting v ddq directly to the 2.5v ra il at the dimm instead of av in and pv in . this ensures that the reference voltage tracks the ddr memory rails precisely without a large voltage drop from the power lines. v sense the purpose of the sense pin is to provide impr oved remote load regulation. in most motherboard applications the termination resistors will connect to v tt in a long plane. if the output voltage was regulated only at the output of the TJ2997 then the long trace will cause a significant ir drop resulting in a termination voltage lower at one end of the bus than the other. the v sense pin can be used to improve this performance, by connect ing it to the middle of the bus. this will provide a better distribution across the entire termination bus. if remote load regulation is not used then the v sense pin must still be connected to v tt . care should be taken when a long v sense trace is implemented in close proximity to the memory. noise pickup in the v sense trace can cause problems with precise regulation of v tt . a small 0.1uf ceramic capacitor placed next to the v sense pin can help filter any high frequency signals and preventing errors. enable the TJ2997 contains an active high enable pin that can be used to tri-state v tt . during shutdown v tt should not be exposed to voltages that exceed avi n. with the enable pin asserted low the quiescent current of the TJ2997 will drop, however, v ddq will always maintain its constant impedance of 100k for generating the internal reference. therefore to calc ulate the total power loss in shutdown both currents need to be considered. for more information refer to the thermal dissipation section. v ref v ref provides the buffered output of the internal reference voltage v ddq / 2. this output should be used to provide the reference voltage for the no rthbridge chipset and memory. since these inputs are typically extremely high impedance, t here should be little cu rrent drawn from v ref . for improved performance, an output bypass capacitor can be used, lo cated close to the pin, to help with noise. a ceramic capacitor in the range of 0.1 f to 0.01 f is recommended. this output remains active during the shutdown state for the suspend to ram functionality. v tt v tt is the regulated output that is used to terminate the bus resistors. it is capable of sinking and sourcing current while regulating the output precisely to v ddq / 2. the TJ2997 is designed to handle peak transient currents of up to 3a with a fast trans ient response at a certain operating condition. if a transient is expected to last above the maximum cont inuous current rating for a significant amount of time then the output capacitor should be sized lar ge enough to prevent an excessive voltage drop. despite the fact that the TJ2997 is designed to handle large transient output current s it is not capable of handling these for long durations, under all conditions. the reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. if large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. proper thermal der ating should always be used (please refer to the thermal dissipation section). if the junction temp erature exceeds the thermal shutdown point than v tt will tri-state until the part returns below the hysteret ic trip-point.
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 7/13 htc thermal dissipation since the TJ2997 is a linear regulator any current flow from v tt will result in internal power dissipation generating heat. to prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate th e part dependent on the maximum expected ambient temperature and power dissipation. the maximu m allowable internal temperature rise, t rmax can be calculated given the maximum ambient temperature, t amax of the application and the maximum allowable junction temperature, t jmax . t rmax = t jmax ? t amax from this equation, the maximum allowable power dissipation , p dmax of the part can be calculated: p dmax = t rmax / ja the maximum allowable value for junction-to-ambient thermal resistance, ja , can be calculated using the formula: ja = t rmax / p d = (t jmax ? t amax ) / p d the ja of the TJ2997 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. for instance, the ja of the sop8 is 165c/w with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5w dissipation at room temperature. this value can be reduced to 152c/w by changing to a 3x4 board with 2 oz. copper that is the jedec standard. additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. using larger traces and more copper on the top side of the board can also help. with careful layout it is possible to reduce the ja further than the nominal values. additional improvements in lowering the ja can also be achieved with a constant airflow across the package. optimizing the ja and placing the TJ2997 in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. the internal power dissipation can be calculated by summing the three main sources of loss: output current at v tt , either sinking or sourcing, and quiescent current at avin and v ddq . during the active state (when enable is not held low) the total internal power dissipation can be calculated from the following equations: p d = p avin + p vddq + p vtt where, p avin = i avin x v avin p vddq = v vddq x i vddq = v vddq2 x r vddq to calculate the maximum power dissipation at v tt both conditions at v tt need to be examined,
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 8/13 htc sinking and sourcing current. although only one equation will add into the total, v tt cannot source and sink current simultaneously. p vtt = v vtt x i load (sinking) or p vtt = ( v pvin - v vtt ) x i load (sourcing) the power dissipation of the TJ2997 can also be calculated during the shutdown state. during this condition the output v tt will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). the only losses during shutdown will be the reduced quiescent current at av in and the constant impedance that is seen at the v ddq pin. p d = p avin + p vddq , where, p avin = i avin x v avin p vddq = v vddq x i vddq = v vddq2 x r vddq
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 9/13 htc typical application information several different application circuits have been shown in figure 2 through figure 11 to illustrate some of the options that are possible in configuring the TJ2997. sstl-2 applications for the majority of applications that implement t he sstl-2 termination scheme it is recommended to connect all the input rails to the 2.5v rail. this provides an optimal trade-off between power dissipation and component count and selection. an example of this circuit can be seen in figure 2. figure 2. recommended sstl-2 implementation if power dissipation or efficiency is a major concern then the TJ2997 has the ability to operate on split power rails. the output stage (pv in ) can be operated on a lower rail such as 1.8v and the analog circuitry (av in ) can be connected to a higher rail such as 2.5v , 3.3v or 5v. this allows the internal power dissipation to be lowered when sourcing current from v tt . the disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard sstl-2 applications. increasing the output capacitance can also help if periods of large load transients will be encountered. figure 3. lower power dissipation sstl-2 implementation the third option for sstl-2 applications in the situati on that a 1.8v rail is not available and it is not desirable to use 2.5v is to connect the tj29 97 power rail to 3.3v. in this situation av in will be limited to operation on the 3.3v or 5v rail as pv in can never exceed av in . this configurati on has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. care should be taken to prevent the TJ2997 from experienci ng large current levels which cause the junction temperature to exceed the maximum. because of th is risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3v rail.
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 10/13 htc figure 4. sstl-2 implementation with higher voltage rails ddr-ii applications with the separate v ddq pin and an internal resistor divider it is possible to use the TJ2997 in applications utilizing ddr-ii memory. figure 3 and figure 4 show several implementations of recommended circuits. figure 3 shows the recommended circuit configuration for ddr-ii applications. the output stage is connected to the 1.8v rail and the av in pin can be connected to either a 3.3v or 5v rail. figure 5. recommended ddr-ii termination if it is not desirable to use the 1.8v rail it is possib le to connect the output stage to a 3.3v rail. care should be taken to do not exceed the maximum junc tion temperature as the thermal dissipation increases with lower v tt output voltages. for this reas on it is not recommended to power pv in off a rail higher than the nominal 3.3v. the adv antage of this configuration is that it has the ability to source and sink a higher maximum continuous current. figure 6. ddr-ii termination with higher voltage rails
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 11/13 htc level shifting if standards other than sstl-2 are required, such as sstl-3, it may be necessary to use a different scaling factor than 0.5 times v ddq for regulating the output voltage. several options are available to scale the output to any voltage requi red. one method is to level sh ift the output by using feedback resistors from v tt to the v sense pin. this has been illustrated in figures 7 and 8. figure 7 shows how to use two resistors to level shift v tt above the internal reference voltage of v ddq / 2. to calculate the exact voltage at v tt the following equation can be used v tt = v ddq / 2 ( 1 + r1 / r2 ) figure 7. increasing vtt by level shifting conversely, the r2 resistor can be placed between v sense and v ddq to shift the v tt output lower than the internal reference voltage of v ddq / 2. the equations relating v tt and the resistors can be seen below: v tt = v ddq / 2 (1 - r1 / r2) figure 8. decreasing vtt by level shifting hstl applications the TJ2997 can be easily adapted for hs tl applications by connecting v ddq to the 1.5v rail. this will produce a v tt and v ref voltage of approximately 0.75v for the te rmination resistors. it is possible to connect pv in to higher than a 2.5v rail for higher source/sink current. care should be taken to do not exceed the maximum junction temperature as t he thermal dissipation increases with lower v tt output voltages (for more information, refer to the ther mal dissipation section.). the advantage of this
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 12/13 htc configuration is that it has the ability to source and sink a higher maximum continuous current. pv in can be also connected to a 1.8v rail and it has a limitation of maximum continuous current. pv in should be connected to a voltage higher than a 1.5v rail. the source/sink current for each power rail, refer to electrical characteristics section. at any power rail, care should be taken to do not exceed the maximum junction temperature as the thermal dissipation increases with lower v tt output voltages as described at the thermal dissipation section. figure 9. hstl application qdr applications quad data rate (qdr) applications utilize multip le channels for improved memory performance. however, this increase in bus lines has the effect of increasing the current levels required for termination. the recommended approach in terminating multiple channels is to use a dedicated TJ2997 for each channel. this simplifies layout and reduces the intern al power dissipation for each regulator. separate v ref signals can be used for each dimm bank from t he corresponding regulator with the chipset reference provided by a local resistor divi der or one of the TJ2997 signals. because v ref and v tt are expected to track and the part to part variations ar e minor, there should be little difference between the reference signals of each TJ2997. figure 10. typical sstl-2 application circuit output capacitor selection for applications utilizing the TJ2997 to terminate sstl-2 i/o signals the typical application circuit shown in figure 8 can be implemented. this circui t permits termination in a minimum amount of board space and component count. capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. however, with motherboards and other applications where
ddr termination regulator TJ2997 apr, 2011 - r1.0.1 13/13 htc v tt is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. figure 9 shown below depicts an example circuit where 2 bulk output capacitors could be situated at both ends of the v tt plane for optimal placement. large aluminum electrolytic capacitors are used for their low esr and low cost. figure 11. typical sstl-2 appl ication circuit for motherboards in most pc applications an extensive amount of decoupling is required because of the long interconnects encountered with the ddr-sdram di mms mounted on modules. as a result bulk aluminum electrolytic capacitors in the range of 1000uf are typically used. pcb layout considerations 1. the input capacitor for the power rail shoul d be placed as close as possible to the pv in pin. 2. v sense should be connected to the v tt termination bus at the point where regulation is required. for mother- board applications an ideal location woul d be at the center of the termination bus. 3. v ddq can be connected remotely to the v ddq rail input at either the dimm or the chipset. this provides the most accurate point for creating the reference voltage. 4. for improved thermal performance excessive top side copper should be used to dissipate heat from the package. numerous vias from the ground connection to the internal ground plane will help. additionally these can be locate d underneath the package if manufacturing standards permit. 5. care should be taken when routing the v sense trace to avoid noise pickup from switching i/o signals. a 0.1uf ceramic capacitor located close to the sense can also be used to filter any unwanted high frequency signal. this can be an issue espe cially if long sense traces are used. 6. v ref should be bypassed with a 0.01f or 0.1f cera mic capacitor for improved performance. this capacitor should be located as close as possible to the v ref pin.

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